(1) Field of the Invention
The present invention relates to the manufacturing of semiconductor devices in general, and in particular, to a method of fabricating a split-gate flash memory cell having salicided control gate and self-aligned contact.
(2) Description of the Related Art
For complementary metal-oxide semiconductor (CMOS) technology with feature sizes less than 0.35 micrometer (xcexcm), it is becoming more and more essential to employ salicidation processes in order to reduce the electrical resistance of device contacts which are dramatically shrinking in size. This follows from the well-known inverse-relationship of resistance to area. At the same time, and commensurate with the scaling down of very large scale (VLSI) and ultra scale integrated (ULSI) devices, it is also becoming essential to employ self-alignment process for forming contacts in the memory cells. Salicidation process is itself a self-aligned silicidation process as will be described below, and the self-aligned contact (SAC) of the memory cell has different requirements than the salicide contacts in the peripheral circuits of a semiconductor memory chip. The salicidation and the SAC processes are usually incompatible. However, a novel process is disclosed in the present invention where the two processes are successfully integrated. To help in the understanding of the invention, some memory cell types and the salicidation process will now be described.
Memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Generally, flash EEPROM cells having both functions of electrical programming and erasing may be classified into two categories, namely, a stack-gate structure and a split-gate structure. A conventional stack-gate type cell is shown in FIG. 1a where, as is well known, tunnel oxide film (20xe2x80x2), a floating gate (30xe2x80x2), an interpoly insulating film (40xe2x80x2) and a control gate (50xe2x80x2) are sequentially stacked on a silicon substrate (10) between a drain region (13xe2x80x2) and a source region (15xe2x80x2) separated by channel region (17xe2x80x2). Substrate (10) and channel region (17xe2x80x2) are of a first conductivity type, and the first (13xe2x80x2) and second (15xe2x80x2) doped regions are of a second conductivity type that is opposite the first conductivity type.
One of the problems that is encountered in flash memory of FIG. 1a is the xe2x80x9cover-erasurexe2x80x9d of the cell contents during erasure operations. In FIG. 1a, the stacked-gate transistor is capable of injecting electrons from drain (13xe2x80x2), based on a phenomenon known as the Fowler-Nordheim Tunneling Effect, through tunneling oxide layer (20xe2x80x2) into floating gate (30xe2x80x2). The threshold voltage of a stacked-gate transistor can be raised by means of such electron injection, and the device is then assumes a first state that reflect the content of the memory cell. On the other hand, during erasure of the memory cell, electrons are expelled from the source (15xe2x80x2) through tunneling oxide layer (20xe2x80x2) and out of floating gate (30xe2x80x2) of the transistor. As a result of this electron removal, the threshold voltage is lowered and thus the device then assumes a second memory state.
During the process of memory content erasure, however, to ensure complete removal of the electrons previously injected, the erasure operation is normally sustained for a slightly prolonged time period. There are occasions when such a prolonged erasure operation results in the removal of excess electrons, i.e., more electrons than were previously injected. This results in the formation of electron holes in the floating gate of the device. In severe cases, the stacked-gate transistor becomes a depletion transistor, which conducts even in the absence of the application of a control voltage at the control gate, (50xe2x80x2). This phenomenon is known in the art as memory over-erasure.
To overcome the described memory over-erasure problem of stacked-gate type EEPROM devices, a split-gate EEPROM device is used as shown in FIG. 1b. This memory device comprises floating-gate transistor which similarly includes control gate (50), floating gate (30) with an intervening interpoly oxide (40) as in the case of the stacked-gate transistor of FIG. 1a. As is usual, gate-oxide (20) separates the floating gate from the substrate. A poly-oxide layer (33) is also usually formed for use as a hard-mask in forming the floating gate (30). However, floating gate (30) here covers only a portion of the channel region, (17), and the rest of the channel region, (19), is directly controlled by control gate (50). This split-gate-based memory cell is equivalent to a series connected floating-gate transistor (17) and an enhanced isolation transistor (19), as is schematically represented in FIG. 1b. The principal advantage of such configuration is that isolation transistor (19) is free from influence of the state of floating gate (17) and remains in its off-state, even if floating-gate transistor (17) is subjected to the phenomenon of over-erasure and therefore, is in a conductive state. The memory cell can thus maintain its correct state irrespective of the over-erasure problem.
In the fabrication of a split-gate flash memory cell such as shown FIG. 1b, it would desirable to use a conventional salicide (self-aligned silicide) process for source/drain contact over regions (13) and/or (15). But that is not possible as will be explained later. The need for salicidation arises from the controlling effect that the physical structure and the electrical characteristics of gate electrode (30) have on the operation of the memory device. Its forming is usually complex and requires exacting processes. Furthermore, materials used for the gate must be compatible with processes that follow up to the completion of the manufacture of the semiconductor devices. With the advent of ULSI (ultra large scale integration) of devices, the shrinking dimensions of the gate as well as the materials used to form the gates have gained even more significance. Thus, if aluminum were to be used as the gate material for example, then, because of its low melting point, it would have to be deposited following the completion of all high-temperature process steps, including drive-in of the source and drain regions. To form the gate electrode in proper relationship to the source/drain, it must be separately aligned with respect to the source and drain. This alignment process adversely affects both packing density and parasitic overlay capacitances between the gate and source/drain regions. For these reasons, it has become a recent practice to use polycrystalline silicon (poly-Si), which has the same high melting point as the silicon substrate, as the gate material. Hence, polysilicon can now be deposited over the gate to form the gate electrode prior to the source and drain formation. Consequently, the gate itself can serve as a mask during formation of the source and drain regions by either diffusion or ion implantation, as is known in the art. Gate (30) thereby becomes nearly perfectly aligned over channel (17) and with respect to source (13) shown in FIG. 1b. The only overlap of the source and drain is due to lateral diffusion of the dopant atoms. This self-alignment feature simplifies the fabrication sequence, increases packing density, and reduces the gate-source and gate-drain parasitic overlap capacitances. For completeness, we note that the threshold voltage, Vth, of MOS device is also favorably affected by the use of polysilicon as the gate electrode material.
On the other hand, polysilicon has much higher electrical resistance as compared to aluminum, for example, and the miniaturization of devices in the ULSI era has exacerbated the electrical properties of the poly-Si gate electrode. Polysilicon is commonly doped by ion implantation to lower the resistivity substantially. However, it is known that polysilicon film has a sheet resistance which is about two orders of magnitude larger than that of aluminum film of the same thickness. The resulting high values of line resistance can lead to long propagation delays and severe dc voltage variations within an ULSI circuit.
In order to overcome the high resistivity problem encountered with polysilicon alone, polycides, a multilayer structure comprising polysilicon and metal silicides are used to form gate electrodes. Silicides are a group of refractory metal compounds (MSix) that are formed by basically three techniques, each of which involves deposition followed by a thermal step to form the silicide: 1) deposition of a pure metal such as tungsten (W), titanium (Ti) or Molybdenum (Mo) on polysilicon, 2) simultaneous evaporation of the silicon and the refractory metal from two sources, and 3) sputter-depositing the silicide itself from a composite target, or by co-sputtering or layering.
In a salicide process, after the polysilicon layers have been deposited and patterned, sidewall spacers (60) are formed. This is accomplished by depositing a layer of oxide (not shown) which conformally covers the polysilicon layers. The oxide layer is then etched back anisotropically until the upper polysilicon layer is exposed. Unetched portions of the oxide at the vertical sides of the polysilicon layers remain following this etch. These residual structures then form the oxide spacers (60) and (60xe2x80x2) shown in FIG. 1b. As practiced conventionally, the metal used to form the silicide (not shown) is deposited and the substrate is next heated, which causes the silicide reaction to occur wherever the metal is in contact with the silicon. Everywhere else, the metal remains unreacted. The unreacted metal at places such as over the spacers is selectively removed through the use of an etchant that does not attack the silicide, the silicon substrate, or the oxide. As a result, in addition to the polysilicon layer, only each exposed source and region is now completely covered by silicide film (not shown) but no other place.
As is well known in the art, the purpose of the spacers is to prevent shorting between metal deposited subsequently on the gate and on the source/drain regions. However, in the split-gate flash memory cell of FIG. 1b, the resulting spacer (60xe2x80x2) next to the floating gate is usually thinner than elsewhere. During the etching of the sidewall spacer, a portion (31) of the floating gate becomes exposed, i.e., the conductive polycrystalline silicon exposed from under the poly-oxide (33). As is commonly practiced in prior art and as explained by Wang in U.S. Pat. No. 5,597,751, an acid dip may be required to remove residual oxide in the silicide area prior to the formation of the salicide layer. The portion (31) of floating gate (30) is therefore exposed more and more. This process leads to the formation of a silicide bridge (or a short circuit) between the floating gate (30) at portion (31) and contact area (14) over source region (13). Hence, salicide process cannot be used successfully.
Salicide and SAC processes are incompatible when used on the same VLSI or ULSI chip where both logic and memory devices are formed. For example, a dynamic random access memory (DRAM) or nonvolatile electrically programmable read only memory (EEPROM), or other similar memory devices are composed of an array of memory cells for storing digital information, while the peripheral circuits on these devices are typically composed of logic circuits for addressing the memory cells, while other peripheral circuits function as read/write buffers and sense amplifiers. Just as salicide and SAC processes are incompatible when used on the same VLSI or ULSI chips where both logic and memory devices are formed, they are especially incompatible when an attempt is made to use them in the same memory cell itself. This is primarily due to the upper level position of the control gate relative to the floating gate of a memory cell where delineation of the silicide area is difficult, as will be seen later in the embodiments of the invention. The present invention discloses an integrated method of using salicide and SAC processes in order to affect scaling down of integrated circuit technology without the aforesaid problems.
In related art, Wang of U.S. Pat. No. 5,597,751 discloses an oxide sealed salicide process to alleviate the problem of bridging in EPROMs. Lee, et al., in U.S. Pat. No. 5,674,767 disclose a method of manufacturing a nonvolatile memory device having a self-aligned structure by initially forming a semiconductor pattern and then removing it at a judiciously chosen process step so that the underlying region becomes the self-aligned source of the split-gate flash memory device. Jeng, et al., in U.S. Pat. No. 5,683,922 use a planarization process that fills a trench between the gates in fabricating a self-aligned contact. A self-aligned ion-implantation method is used by Yeh of U.S. Pat. No. 5,242,848 for making a split-gate single transistor nonvolatile electrically alterable semiconductor memory cell. Yeh also discloses in U.S. Pat. No. 5,045,488 another method of making an electrically programmable and erasable memory device having a re-crystallized floating gate. Ahn of U.S. Pat. No. 5,652,161, on the other hand, discloses a method of making split gate flash EEPROM cell by providing a thick insulating film to prevent degradation of the tunnel oxide film of the cell.
Thus, prior art provides methods of forming salicides and SACs. The present invention discloses a process where the two methods can be successfully integrated in the manufacturing of split-gate flash memory devices.
It is therefore an object of the present invention to provide a novel split-gate flash cell for salicide and self-align contact (SAC).
It is another object of the present invention to provide a method of forming salicided control gate and SAC.
It is yet another object of the present invention to provide a method of forming an upper level oxide layer in conjunction with oxide spacers to form a salicidated control gate in a split-gate flash memory cell.
These objects are accomplished by providing a semiconductor substrate having active and passive region defined; forming a gate oxide layer on said semiconductor substrate; forming a first polysilicon layer over said gate oxide layer; forming a nitride layer over said first polysilicon layer; forming a first photoresist mask having floating gate pattern over said nitride layer; etching through said floating gate pattern in said first photoresist mask to form openings in said nitride layer and exposing said first polysilicon layer at the bottom of said openings; removing said first photoresist mask; oxidizing said exposed first polysilicon layer at the bottom of said openings in said nitride layer to form poly-oxide; removing said nitride layer; using said poly-oxide as a hard-mask, etching said first polysilicon layer to form a floating gate underlying said poly-oxide layer; forming an interpoly oxide layer over said substrate; forming a second polysilicon layer over said interpoly oxide layer; ion implanting said second polysilicon layer; forming an oxide layer over said second polysilicon layer; forming a partial hard photomask over said oxide layer having open pattern over gate region; etching through said open pattern in said partial hard mask to remove portions of said oxide layer exposed in said open pattern; removing said partial hard photomask; forming a second photoresist mask having control gate pattern over said second polysilicon layer; etching through pattern in said second photoresist mask to form a control gate; performing ion implantation to form source region; forming nitride spacer; performing ion implantation to form drain region; depositing a resistor protecting oxide (RPO) layer over said substrate; etching said RPO to form openings over gate and contact surfaces of substrate where salicidation is to be performed; performing salicidation in said openings; forming an interlevel dielectric layer (ILD) over said substrate; forming a third photoresist mask having self-aligned contact pattern over said ILD; etching through said pattern in said third photoresist mask to form self-aligned contact opening in said ILD layer; forming metal in said self-aligned contact openings and performing etch back to complete the forming of said split-gate having salicidated gate and self-aligned contacts.